How is Internal Block Arrangement of 555?

555 Timer IC is a highly stable controller capable of producing accurate time delays, or oscillation to adopt itself into various applications.

It has dual comparators and flip-flop which will make this IC operated in three different modes i.e. Astable mode, Monostable mode, and Bistable (Schimitt) mode.

So in this post we are going to learn about 555 timer IC, internal block arrangment with each block function, applications, and many more.

Pin configuration of IC 555

  1. GND - Ground reference voltage, low level (0 V).
  2. Trigger - Responsible for the transition of the flip-flop from set to reset.
  3. Output - Connected to load as it is the only pin with output driven waveform.
  4. Reset - Negative pulse applied to this pin to disable or reset the timer.
  5. Control - Controls the threshold and trigger levels.
  6. Threshold - Compares the voltage applied to the terminal with a reference voltage of 2/3 VCC.
  7. Discharge - Open collector output which discharges a capacitor between intervals (in phase with output).
  8. VCC - Supply Voltage (Typical = 5V, Maximum = 18V).

555 Timer Internal Block Arrangement

The functional block diagram and 555 timer connection diagram are shown below.

Why is IC 555 called 555? - There are three resistors of value 5KΩ internally connected, uses to generate the two comparators reference voltages which give this IC it's iconic name "555 Timer".

Function of each Block

IC 555 timer has two comparators which receive their reference voltage by a combination of three resistance of each valve R connected between the supply voltage VCC and ground.

The reference voltage for comparator 1 is 2VCC/3 and for comparator 2 is VCC/3.

During the negative-going excursion the trigger input passes through the reference voltage VCC/3, which makes the output of the comparator 2 high and the flip-flop sets to 1 (Q = 1).

Similarly on a positive-going excursion, the threshold voltage passes through the reference voltage 2VCC/3, which makes the output of the comparator 1 high, and this results the flip-flop reset to zero (Q' = 1).

A timing capacitor of magnitude C is to be connected between the ground and discharge terminal (pin no. 7).

When the R-S flip-flop is in reset condition, its Q' = 1, which makes transistor T1 to saturation there by discharging the timing capacitor.

But when the R-S flip-flop goes to set condition then the transistor T1 is off.

The time constant for the charging of the timing capacitopr T = RA × C, where RA is a resistor to be connected between the VCC and discharge terminal and C is the timing capacitor.

Therefore the transistor T1 is off where the output is at logic 1 and at logic 0, the transistor T1 is on.

The load can be connected either between the output terminal and ground terminal or between the output terminal and VCC terminal.

Applications of 555 Timer IC

  • Time Delay Generation
  • Pulse Width Modulation (PWM)
  • Pulse generation
  • Precision Timing
  • Pulse Position Modulation (PPM)
  • Linear Ramp Generator
  • Sequential Timing circuits


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